This invention relates to a digital signal input circuit constituted by a semiconductor integrated circuit, and more particularly, to a signal input circuit suitable for use in a MOS memory integrated circuit and in MOS logical integrated circuit design.
Static Random Access Memory (hereinafter referred to a "SRAM") devices include an address transition detector, which is non-synchronous with an outer circuit and synchronous with an inner circuit. These have been developed for decreasing power consumption while increasing the packaging density. For achieving high speed while increasing packaging density, there has been developed the SRAM Large Scale Integrated Circuit (hereinafter referred to as "LSI"). However, problems occur in SRAM involving the address transition detector. These problems relate to a peak current of the power source flowing when the chip enable signal changes. A malfunction of a signal input circuit in a Row Address Buffer circuit is one cause of such problems.
FIG. 1 (PRIOR ART) shows a Row Address Buffer circuit having the signal input circuit conventionally used in MOS LSI Memory circuits. FIG. 2 (PRIOR ART) shows signals used in the signal input circuit of FIG. 1.
In FIG. 1, a signal input circuit 1 includes a NOR gate 2 which goes high at a disable state of CE, used as an enable control signal. Since the output of NOR gate 2 is normally clamped to a low level at a disable state, the current path between the power source V.sub.DD (not shown) of the gate 2 and the ground potential V.sub.SS (not shown) is interrupted.
There is no problem when the input signal (i) is high and the enable control signal CE is in the enable state. The output (A) of NOR gate 2 continues to be low and the output of the signal input circuit 1 does not change when the enable control signal CE changes to a low level from a high level, or to a high level from a low level. An internal circuit inputted by the output of NOR gate 2 is not activated and no power consumption is caused. However, a problem occurs when the input signal (i) is low when the enable control signal CE changes to a high level from a low level. That is because the output (node A) of NOR gate 2 changes to a low level from a high level when the enable control signal CE changes to a high level. This signal is the same signal that would be generated if the input signal (i) were to change to a high level. The change of (A) from low to high level is propagated in the internal circuit, such as for example, an address pre-decoder 4, and an address transition detector 6. As a result, the internal circuit is activated and power consumption is caused thereby. After that, when the enable control signal CE changes to the low level (enable state) and the input signal (i) is a low level, the output (A) of NOR gate 2 changes to a high level from a low level. This change of the signal is transmitted to the internal circuit. The delay time for this change is the same time as that required for a change of the input signal i.
Furthermore, when the delay time from the formation of the enable control signal CE by a chip input control signal to its arrival at the input gate of circuit 1 shown in FIG. 1 is included, the access time, in the case where the internal circuit is accessed by the change in control signal CE, is delayed as compared with the time required when the signal input was changed, notwithstanding the fact that the signal input is not changed at low level. The changes occur in each of the gates from the input stage to the internal circuit, whereby a large amount of electric power is consumed.
Furthermore, as shown in FIG. 1, when the enable control signal CE changes slowly and the output B of the signal input circuit 1 crosses a response voltage of the transition detector 6, an output of the address transition detector changes. As a result, bit lines of the LSI memory are pre-charged as a bit line signal .phi..sub.ij changes, and the read operation occurs and the data output buffers are activated. A large amount of current flows through some circuits in MOS LSI for this pre-charge. A power source noise is generated in MOS LSI for this current. The electric potential of node B is fluctuated by the power source noise. Then, since the output of the signal input circuit crosses the response voltage, the transition detector responds again. By this phenomenon the bit lines are precharged, the power source noise is generated and the electric potential of node B is fluctuated again. This process is repeated many times. The pre-charge and the read operation is repeated and the electric power is wasted. In MOS LSI memory, when the enable control signal CE is the disable state, the MOS LSI memory is usually supported by a battery back-up system. However, the power consumption caused by the abnormal operation mentioned above cannot be corrected by the battery back-up system.